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Synopsys, Inc. Senior II Product Engineer in Denver, Colorado

Senior II Product Engineer27988BRUSA - Arizona - Chandler, USA - Arizona - Tucson, USA - California -California, USA - California - Folsom, USA - California - Irvine, USA -California - Los Angeles, USA - California - Mountain View/Sunnyvale,USA - California - Pasadena, USA - California - San Diego, USA -California - San Francisco, USA - California - San Jose, USA - Colorado -Denver, USA - Colorado - Longmont, USA - Colorado - Westminster, USA -Texas - Austin, USA - Texas - Dallas, USA - Texas - Plano, USA -Washington - Bellevue, USA - Washington - SeattleThe will be an expert in Physical Design methodologies and flows to supportthe development and adoption of Synopsys Digital Implementation products tohelp customers achieve best Power, Performance, Area and Runtime amongother metrics for their projects. Deep understanding of Synthesis (logicaland physical) is required and understanding of Formal Verification andStatic Timing Analysis (STA) knowledge is desirable. Experience withphysical design implementation of blocks is required. Hands-on experience inall aspects of physical design implementation of blocks including placement,clock tree synthesis, routing and timing closure is required. Knowledge offloorplanning, multi voltage design, top level integration and DRC closureis preferred. In addition, you are expected to be able to articulate designmethodologies and drive development with RandD teams. You are expected tomanage multiple customer activities and internal development concurrently,and work with field and RandD teams to set their priorities.Requirements:Hands-on experience in all aspects of physical design including datapreparation, placement, clock tree synthesis, routing,floorplanning, timing and DRC closure, and low power physical implementation.Experience with modern technology nodes (16nm and below) is required.Must possess at least three years of recent hands on experience in the placeand route domain using Synopsys or competing PlaceandRoute tools (ICCompiler II/Fusion Compiler experience is preferred).Knowledge of areas ASIC implementation domains outside of place and route,including logic synthesis, static timing analysis, equivalence checking,parasitic extraction, DRC/LVS and power analysis is a plus.Excellent verbal and written communication skills are required.Customer sensitivity, the ability to multiplex many issues and setpriorities, and the desire to help customers exploit new technologies areessential for success in the position.BSEE or equivalent, required with 5 years of experience, or MSEE, orequivalent with 3 years of experience.At Synopsys, we're at the heart ofthe innovations that change the way we work and play. Self-driving cars.Artificial Intelligence. The cloud. 5G. The Internet of Things. Thesebreakthroughs are ushering in the Era of Smart Everything. And we'repowering it all with the world's most advanced technologies for chip designand software security. If you share our passion for innovation, we want tomeetOur Silicon Design business is all about building high-performance siliconchips-faster. We're the world's leading provider of solutions fordesigning and verifying advanced silicon chips. And we design thenext-generation processes and models needed to manufacture those chips. Weenable our customers to optimize chips for power, cost, andperformance-eliminating months off their project schedules.Inclusion and Diversity are important to us. Synopsys considers all applicantsfor employment without regard to race, color, religion, nationalorigin, gender, sexual orientation, gender identity, age, militaryveteran status, or disability.#LI-SV1Job CategoryEngineeringHire TypeEmployeeCountryUnited StatesSynopsys maintains a workplace where all personnel, customers, and vendorsare treated with dignity, fairness, and respect. We maintain worldwidepolicies in our Work Rules Policy, which is applicable to all employees infurtherance of these principles. We pride ourselves on providing a healthy andpr

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